1. Field of the Invention
This invention relates generally to the processing of analog signals and, more particularly, to the processing to analog signal which have been converted to a digital representation. The particular digital representation used by the present invention involves the use of residue numbers derived from the analog signal of the full digital representation of a signal.
2. Description of the Related Art
It is known in the prior art to perform complex processing operations on digital signals by first converting the incoming analog signals to a digital representation and the performing the processing operations on the analogs signals in the digital representation. Referring for example to FIG. 1, a block diagram of an FIR (finite integer response) filter is shown. The INCOMING SIGNAL is applied to an analog/digital (A/D) converter 11 wherein the analog signal is divided into a series of sequential portions (i.e., in time) and each portion is converter to a sequence of digital signal representations. Each digital signal representation applied to filter unit 12 where the digital signal representation is transmitted through a series of delay lines 121. The sequential digital signal representation in each delay unit 121 is applied to a multiplier 122 wherein the digital signal representation stored in the coupled delay unit 121 is multiplied by a weighting factor. The output signal from each multiplier unit 122 is applied to a series of summation units 123. The output signal of each summation unit 123 is applied to the summation unit 123 coupled through a multiplier unit to the next sequential delay unit 121. The output signal of filter unit 12 can then be applied to a digital-to-analog converter unit 13 or can be used without conversion in further signal processing operations.
Referring to FIG. 3, an analog-to-digital converter unit 31 according to the prior art is shown. The digital-to-analog converter unit generates a digital binary output signal determined by the magnitude of the input signal. In this configuration, an ANALOG INPUT SIGNAL is applied to a series of comparator units 311. A second input terminal of the comparator units 311 receive a hierarchy of reference voltages determined in FIG. 3 by a series of resistors. The highest comparator activated by the ANALOG INPUT SIGNAL and applying a signal to the encoder unit 313 determines the DIGITAL OUTPUT SIGNAL.
When the typical normal digital representation is used, each arithmetic operation is implemented by a complex logic unit. And in many processing operations, such as that shown with the FIR filter, a large number of implementing units are required. Furthermore, the functions require a substantial amount of time to perform because of the possibility of carry bit propagation along a sequence of binary digits.
A need has therefore been felt for apparatus and a related method which would permit the implementation of arithmetic operations, for the digital processing of signals, which uses relatively simple apparatus and which does not include carry signal propagation along a series of binary numbers.